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Run RISC-V Binaries on AMD Zen-series CPUs via Microcode Modification

S2502
CNY 20,000
1
2025-03-06 (AoE)
2025-06-06 (AoE)

This content has been machine-translated. In case of any discrepancies or ambiguities, the original Chinese version shall prevail.

Challenge Description​

Current AMD Zen-series CPUs (e.g., EPYC 9004 series) have begun integrating RISC-V coprocessors for specific acceleration tasks. The microcode of AMD Zen-series processors enables modification of low-level CPU instruction execution behavior through software-level firmware patches, making it suitable for optimizing instruction execution and altering specific instruction behaviors. Zentool, developed by Google's Security Research team, is a toolkit for analyzing, modifying, and generating microcode patches for AMD Zen-series processors.

Rubrics​

  1. Microcode Patch: Complete microcode modifications for Zen-series CPUs to enable direct execution of RISC-V binary programs. If direct execution is not feasible, optimize the modified microcode to achieve a significant level of acceleration for RISC-V binaries.
  2. Performance Optimization Testing: Run RISC-V binary versions of benchmark applications (e.g., Coremark, Dhrystone) on Zen-series CPUs. Compare performance against simulator-based RISC-V emulation on the same hardware, ensuring measurable and substantial performance improvements.
  3. Documentation:
    • Document the rationale behind microcode modifications.
    • Outline methodologies for accelerating RISC-V binaries.
    • Detail testing procedures and benchmark results.

Important Notes

  • Ensure compliance with open-source licenses and copyright regulations.
  • Participants must prepare their own development environment with required tools/libraries.

Platform​

  • AMD Zen-series CPUs

Submission​

  1. The submission repository is https://github.com/rv2036/rvspoc-P2501-v4l2
  2. Submit results via Pull Request (PR) to the above repository:
    • All references to "PR" in subsequent conditions refer to Pull Requests against the repository in Condition 1.
  3. When creating a PR, provide necessary materials for reproducing the porting results, including but not limited to:
    • Complete source code or binaries *
    • Configuration files (if applicable)
    • Additional library files (if applicable)
    • Extra patches (if applicable)
    • Other materials essential for verifying the submission
  4. When creating a PR, include a documentation file specifying verification details, including but not limited to:
    • Platform requirements (if any): OS name, version, and installation instructions
    • Dependency requirements (if any): Library details and installation guidance
    • Compilation & installation procedures
    • Execution steps
    • Expected runtime results
    • Other verification-critical information
  5. This is a porting challenge:
    • For the first item in Condition 3 (*), participants must submit all source code via PR before 2025 年 6 月 7 日 (AoE) (end of day) to complete the challenge.
  6. The organizing committee will begin verification within 24 hours of PR submission.

Assessment​

  • Details will be announced by the RVSPOC Organizing Committee after June 7.
  • Due to the open-ended nature of the challenge and the complexity of the software, there may be unexplained or incomplete aspects in the initial release. Adjustments may be made based on participant feedback during the competition. Please monitor the official event website for updates. Final interpretations and decisions rest with the competition's Problem Review Committee.

Notice on Intellectual Properties and Open Source Licenses​

All challenge submissions must be open source and committed to a specified repository. The participant(s) (author) holds rights to their work. The host encourages contributing any changes made to the upstream.